MPC8377E datasheet(46/126 Pages) FREESCALE

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MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Enhanced Secure Digital Host Controller (eSDHC)

11.2.1

Full-Speed Output Path (Write)

Figure 27 provides the data and command output timing diagram.

Figure 27. Full Speed Output Path

11.2.1.1

Full-Speed Write Meeting Setup (Maximum Delay)

The following equations show how to calculate the allowed skew range between the SD_CLK and

SD_DAT/CMD signals on the PCB.

No clock delay:

tSFSKHOV + tDATA_DELAY + tISU < tSFSCKL

Eqn. 1

With clock delay:

tSFSKHOV + tDATA_DELAY + tISU < tSFSCKL + tCLK_DELAY

Eqn. 2

tDATA_DELAY + tSFSCKL < tSFSCK + tCLK_DELAY – tISU – tSFSKHOV

Eqn. 3

This means that data can be delayed versus clock up to 11 ns in ideal case of tSFSCKL =20ns:

tDATA_DELAY + 20 < 40 + tCLK_DELAY – 5 – 4

tDATA_DELAY < 11 + tCLK_DELAY

11.2.1.2

Full-Speed Write Meeting Hold (Minimum Delay)

The following equations show how to calculate the allowed skew range between the SD_CLK and

SD_DAT/CMD signals on the PCB.

tCLK_DELAY < tSFSCKL + tSFSKHOX + tDATA_DELAY – tIH

Eqn. 4

Input at the

MPC8377E Pins

SD CLK at the

MPC8377E Pin

Output Valid Time: tSFSKHOV

Output Hold Time: tSFSKHOX

tIH (5 ns)

tCLK_DELAY

SD CLK at

Driving

Edge

Sampling

Edge

the Card Pin

tISU (5 ns)

tDATA_DELAY

tSFSCKL

tSFSCK (Clock Cycle)

Output from the

MPC8377E Pins

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