MPC8378E datasheet(30/127 Pages) FREESCALE

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

8.3.2

AC Requirements for SGMII L1_SD_REF_CLK and L1_SD_REF_CLK

Table 30 lists the AC timing specifications. Note that L1_SD_REF_CLK and L1_SD_REF_CLK are not

intended to be used with, and should not be clocked by, a spread spectrum clock source.

8.3.3

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.3.3.1

MII Transmit AC Timing Specifications

Table 31 provides the MII transmit AC timing specifications.

Table 30. L1_SD_REF_CLK and L1_SD_REF_CLK AC Requirements

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

L1_SD_REF_CLK/_B reference clock cycle time

100 MHz

125 MHz

tCK_REF

—

—ns

1, 2

L1_SD_REF_CLK/_B rise/fall time (80%-20%)

tCK_RISE/tCK_FALL

——

—

L1_SD_REF_CLK/_B duty cycle (@50% L1_nVDD)tck_dty

45%

—

55%

—

L1_SD_REF_CLK/_B cycle to cycle clock jitter (period

jitter)

tCKCJ

——

100

—

L1_SD_REF_CLK/_B phase jitter peak-to-peak.

Deviation in edge location with respect to mean edge

location.

tCKPJ

–50

—

Note:

1 Both options provide serial interface bit rate of 1.25 Gbps. 8 ns only applies when 125 MHz SerDes1 clock frequency is

selected during POR.

2 Tolerance of ±100 ppm.

Table 31. MII Transmit AC Timing Specifications

At recommended operating conditions with LVDD of 3.3 V ± 5%.

Parameter

Symbol1

Min

Typical

Max

Unit

TX_CLK clock period 10 Mbps

tMTX

—

400

—

TX_CLK clock period 100 Mbps

tMTX

—40—

TX_CLK duty cycle

tMTXH/tMTX

—

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

tMTKHDX

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