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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MPC8378E 데이터시트(PDF) 49 Page - Freescale Semiconductor, Inc |
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MPC8378E 데이터시트(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 127 page  MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4 Freescale Semiconductor 49 Enhanced Secure Digital Host Controller (eSDHC) Figure 29. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Bypass Mode) 11 Enhanced Secure Digital Host Controller (eSDHC) This section describes the DC and AC electrical specifications for the eSDHC (SD/MMC) interface of the MPC8378E. The eSDHC controller always uses the falling edge of the SD_CLK in order to drive the SD_DAT[0:3]/CMD as outputs and sample the SD_DAT[0:3] as inputs. This behavior is true for both full- and high-speed modes. Note that this is a non-standard implementation, as the SD card specification assumes that in high-speed mode, data is driven at the rising edge of the clock. LCLK UPM Mode Input Signal: LUPWAIT tLBIXKH tLBIVKH tLBIVKH tLBIXKH T1 T3 GPCM Mode Output Signals: LCS[0:7]/LWE[0:3] tLBKHOV tLBKHOZ T2 T4 Input Signals: LAD[0:31] UPM Mode Output Signals: LCS[0:7]/LBS[0:1]/LGPL[0:5] tLBKHOV Output (Data) Signals: LAD[0:31]/LDP[0:3] Output (Address) Signal: LAD[0:31] tLBKHOZ tLBKHOZ tLBKHOV tLBKHOV |
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