MPC8535E datasheet(29/126 Pages) FREESCALE

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Input Clocks

MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

2.4.4

eTSEC Gigabit Reference Clock Timing

Table 8 provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications for the MPC8535E.

2.4.5

DDR Clock Timing

Table 9 provides the DDR clock (DDRCLK) AC timing specifications for the MPC8535E.

Table 8. EC_GTX_CLK125 AC Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

EC_GTX_CLK125 frequency

fG125

—

125

—

MHz

—

EC_GTX_CLK125 cycle time

tG125

—8

—

EC_GTX_CLK rise and fall time

LVDD, TVDD = 2.5V

LVDD, TVDD = 3.3V

tG125R/tG125F

——

0.75

1.0

EC_GTX_CLK125 duty cycle

GMII, TBI

1000Base-T for RGMII, RTBI

tG125H/tG125

—

Notes:

1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for L/TVDD=2.5V, and from 0.6 and 2.7V for

L/TVDD=3.3V at 0.6 V and 2.7 V.

2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. EC_GTX_CLK125

duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC

GTX_CLK. See Section 2.9.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and 100Base-T

reference clock.

Table 9. DDRCLK AC Timing Specifications

At recommended operating conditions with OVDD of 3.3V ± 5%.

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

DDRCLK frequency

fDDRCLK

—

166

MHz

DDRCLK cycle time

tDDRCLK

6.0

—

15.15

—

DDRCLK rise and fall time

tKH, tKL

0.61.01.2ns

DDRCLK duty cycle

tKHK/tDDRCLK

—

DDRCLK jitter

—

+/– 150

3, 4

Notes:

1. Caution: The DDR complex clock to DDRCLK ratio settings must be chosen such that the resulting DDR complex

clock frequency does not exceed the maximum or minimum operating frequencies. See Section 2.23.4,

“DDR/DDRCLK PLL Ratio,” for ratio settings.

2. Rise and fall times for DDRCLK are measured at 0.6 V and 2.7 V.

3. The DDRCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to

allow cascade-connected PLL-based devices to track DDRCLK drivers with the specified jitter.

4. For spread spectrum clocking, guidelines are +0% to –1% down spread at a modulation rate between 20 kHz and

60 kHz on DDRCLK.

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