MPC8535E datasheet(102/126 Pages) FREESCALE

102 / 126 page

MPC8535E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 3

PCI Express

Freescale Semiconductor

102

2.21.4.2

Transmitter Compliance Eye Diagrams

The TX eye diagram in Figure 69 is specified using the passive compliance/test measurement load (see Figure 71) in place of

any real PCI Express interconnect + RX component.

There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time using the jitter

median to locate the center of the eye diagram. The different eye diagrams will differ in voltage depending whether it is a

transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit will always be relative to the

transition bit.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges

of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.

NOTE

It is recommended that the recovered TX UI is calculated using all edges in the 3500

consecutive UI interval with a fit algorithm using a minimization merit function (that is,

least squares and median deviation fits).

Figure 69. Minimum Transmitter Timing and Voltage Output Compliance Specifications

2.21.4.3

Differential Receiver (RX) Input Specifications

Table 72 defines the specifications for the differential input at all receivers (RXs). The parameters are specified at the

component pins.

Table 72. Differential Receiver (RX) Input Specifications

Symbol

Parameter

Min

Nom

Max

Units

Comments

Unit Interval

399.8

400

400.12

Each UI is 400 ps ± 300 ppm. UI does not

account for Spread Spectrum Clock dictated

variations. See Note 1.

VRX-DIFFp-p

Differential

Peak-to-Peak

Output Voltage

0.175

—

1.200

VRX-DIFFp-p = 2*|VRX-D+ – VRX-D-|

See Note 2.

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