AT89LP51 datasheet(78/113 Pages) ATMEL

78 / 113 page

3709B–MICRO–12/10

AT89LP51/52 - Preliminary

Notes:

1. A clock cycle is one period of the output of the system clock divider. For Fast mode the divider

defaults to 1, so the clock cycle equals the oscillator period. For Compatibility mode the divider

defaults to 2, so the clock cycle is twice the oscillator period, or conversely the clock count is

half the number of oscillator periods.

2. This escaped instruction is an extension to the instruction set.

3. This is the minimum time for MOVX with no wait states. In Compatibility mode an additional 24

clocks are added for the wait state. In Fast mode, 1 clock is added for each wait state (0–3).

ORL C, bit

ORL C, /bit

MOV C, bit

MOV bit, C

Branching

Bytes

Clock Cycles

Hex Code

Compatibility

Fast

JC rel

JNC rel

JB bit, rel

JNB bit, rel

JBC bit, rel

JZ rel

JNZ rel

SJMP rel

ACALL addr11

11,31,51,71,91,

B1,D1,F1

LCALL addr16

RET

RETI

AJMP addr11

01,21,41,61,81,

A1,C1,E1

LJMP addr16

JMP @A+DPTR

JMP @A+PC(2)

212

A5 73

CJNE A, direct, rel

CJNE A, #data, rel

CJNE Rn, #data, rel

B8-BF

CJNE @Ri, #data, rel

B6-B7

CJNE A, @R0, rel

(2)

318

4A5 B6

CJNE A, @R1, rel(2)

318

4A5 B7

DJNZ Rn, rel

D8-DF

DJNZ direct, rel

NOP

Table 16-1.

Instruction Execution Times and Exceptions

(1) (Continued)

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