4-Level FSK Modem Data Pump

FX929A

© 1996 Consumer Microcircuits Limited

23

D/929A/4

B3

B2

Mode

0

0

Hold

0

1

Slow Peak Detect

1

0

Lossy Peak Detect

1

1

Clamp

In normal use the LEVRES bits should be set to 'Slow Peak Detect', the other modes are intended for special

test purposes or are invoked automatically during an AQLEV sequence.

In the 'Slow' and 'Lossy' Peak Detect modes the positive and negative excursions of the received signal (after

filtering) are measured by peak rectifiers driving the DOC1 and DOC2 capacitors, to establish the amplitude of

the signal and any dc offset wrt VBIAS . The peak rectifiers are disabled in 'Hold' mode.

In 'Clamp' mode the DOC1 and DOC2 pins are connected directly to the output of the circuit that normally

drives the peak detectors.

Control Register B1, B0: PLLBW - Phase-Locked Loop Modes

These two bits have no effect in transmit mode. In receive mode, they set the 'normal' bandwidth of the Rx

clock extraction Phase Locked Loop circuit. This setting will be temporarily overridden by the automatic

sequencing of an AQSC command.

B1

B0

PLL Mode

0

0

Hold

0

1

Narrow Bandwidth

1

0

Medium Bandwidth

1

1

Wide Bandwidth

The normal setting for the PLLBW bits should be 'Medium Bandwidth' when the received symbol rate and the

frequency of the receiving modem's Xtal are both within ±100ppm of nominal, except at the start of a symbol

clock acquisition sequence (AQSC) when 'WIde Bandwidth' should be selected as described in section 1.6.3.

If the received symbol rate and Xtal frequency are both within ±20ppm of nominal then selection of the 'Narrow

Bandwidth' setting will give better performance, especially through fades or noise bursts which might otherwise

pull the PLL away from its optimum timing, but in this case it is recommended that the PLLBW bits are only set

to 'Narrow Bandwidth' after the modem has been running in 'Medium Bandwidth' mode for about 200 symbol

times.

The 'Hold' setting disables the feedback loop of the PLL, which continues to run at a rate determined only by

the actual Xtal frequency and the setting of the Control Register CKDIV bits.

1.5.5.4 Mode Register

The contents of this 8-bit write only register control the basic operating modes of the modem: