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AD7466 데이터시트(PDF) 19 Page - Analog Devices |
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AD7466 데이터시트(HTML) 19 Page - Analog Devices |
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19 / 28 page ![]() AD7466/AD7467/AD7468 Rev. C | Page 19 of 28 NORMAL MODE The AD7466/AD7467/AD7468 automatically enter power- down at the end of each conversion. This mode of operation is designed to provide flexible power management options and to optimize the power dissipation/throughput rate ratio for low power application requirements. Figure 24 shows the general operation of the AD7466/AD7467/AD7468. On the CS falling edge, the part begins to power up and the track-and-hold, which was in hold while the part was in power-down, goes into track mode. The conversion is also initiated at this point. On the third SCLK falling edge after the CS falling edge, the track- and-hold returns to hold mode. For the AD7466, 16 serial clock cycles are required to complete the conversion and access the complete conversion result. The AD7466 automatically enters power-down mode on the 16th SCLK falling edge. For the AD7467, 14 serial clock cycles are required to complete the conversion and access the complete conversion result. The AD7467 automatically enters power-down mode on the 14th SCLK falling edge. For the AD7468, 12 serial clock cycles are required to complete the conversion and access the complete conversion result. The AD7468 automatically enters power-down mode on the 12th SCLK falling edge. The AD7466 also enters power-down mode if CS is brought high any time before the 16th SCLK falling edge. The conver- sion that was initiated by the CS falling edge terminates and SDATA goes back into three-state. This also applies for the AD7467 and AD7468; if CS is brought high before the conver- sion is complete (the 14th SCLK falling edge for the AD7467, and the 12th SCLK falling edge for the AD7468), the part enters power-down, the conversion terminates, and SDATA goes back into three-state. Although CS can idle high or low between conversions, bringing CS high once the conversion is complete is recom- mended to save power. When supplies are first applied to the devices, a dummy conver- sion should be performed to ensure that the parts are in power- down mode, the track-and-hold is in hold mode, and SDATA is in three-state. Once a data transfer is complete (SDATA has returned to three- state), another conversion can be initiated after the quiet time, tQUIET, has elapsed, by bringing CS low again. THE PART BEGINS TO POWER UP AD7468 ENTERS POWER-DOWN AD7467 ENTERS POWER-DOWN AD7466 ENTERS POWER-DOWN VALID DATA SCLK SDATA 12 3 12 14 16 THE PART IS POWERED UP AND VIN FULLY ACQUIRED CS Figure 24. Normal Mode Operation |
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