13892 datasheet(78/156 Pages) FREESCALE

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S W1 P WM Pu lse S kip pi ng mo de E ffi ciency Vo ut = 0, 725 V

10 %

20 %

30 %

40 %

50 %

60 %

70 %

80 %

90 %

100 %

1 0203 0

5060

7080

10 0

Ilo a d (m A)

Vin = 3 ,00 0 V

Vin = 3 ,60 0 V

Vin = 4 ,65 0 V

S W1 PWM P ulse Ski ppi ng mo de E ffi ciency Vo ut = 0, 725 V

10 %

20 %

30 %

40 %

50 %

60 %

70 %

80 %

90 %

100 %

1 00 150 200 25 0 300 35 0 4 00 450 50 0 55 0 6 00 650 70 0 7 50 800 85 0 90 0 9 50 10 0

105

Il oa d (m A)

Vin = 3,0 00 V

Vin = 3,6 00 V

Vin = 4,6 50 V

S W2 P WM Pu lse S kip pi ng mo de E ffi ciency Vo ut = 1. 250 V

10 %

20 %

30 %

40 %

50 %

60 %

70 %

80 %

90 %

100 %

1 0203 0

5060

7080

10 0

Ilo a d (m A)

Vin = 3 ,00 0 V

Vin = 3 ,60 0 V

Vin = 4 ,65 0 V

S W2 P WM Pu lse S kip pin g m od e E ffici ency V ou t = 1.250 V

10 %

20 %

30 %

40 %

50 %

60 %

70 %

80 %

90 %

100 %

1 00

1 50

20 0

25 0

300

350

4 00

4 50

50 0

55 0

600

650

7 00

7 50

80 0

85 0

900

Ilo a d (m A)

Vin = 3, 000 V

Vin = 3, 600 V

Vin = 4, 650 V

S W4 P WM Pu lse S kip pi ng mo de E ffi ciency Vo ut = 1. 800 V

10 %

20 %

30 %

40 %

50 %

60 %

70 %

80 %

90 %

100 %

1 0203 0

5060

7080

10 0

Ilo a d (m A)

Vin = 3 ,00 0 V

Vin = 3 ,60 0 V

Vin = 4 ,65 0 V

S W4 PWM P ulse Ski ppi ng mo de E ffi ciency Vo ut = 1. 800 V

10 %

20 %

30 %

40 %

50 %

60 %

70 %

80 %

90 %

100 %

1 00

1 50

20 0

2 50

30 0

35 0

400

450

5 00

5 50

60 0

65 0

700

750

8 00

850

9 00

Il oa d (m A)

Vin = 3,0 00 V

Vin = 3,6 00 V

Vin = 4,6 50 V

Analog Integrated Circuit Device Data

Freescale Semiconductor

13892

FUNCTIONAL DEVICE OPERATION

SUPPLIES

Figure 19. Buck Switcher PWM (Pulse Skipping) Efficiency

DYNAMIC VOLTAGE SCALING

To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the

processor. SW1 and SW2 allow for three different set points with controlled transitions to avoid sudden output voltage changes,

which could cause logic disruptions on their loads. Preset operating points for SW1 and SW2 can be set up for:

• Normal operation: output value selected by SPI bits SWx[4:0]. Voltage transitions initiated by SPI writes to SWx[4:0] are

governed by the same DVS stepping rate that is programmed for DVSx pin initiated transitions.

• DVS: output can be higher or lower than normal operation for tailoring to application requirements. Configured by SPI bits

SWxDVS[4:0] and controlled by a DVSx pin transition.

• Standby (Deep Sleep): can be higher or lower than normal operation, but is typically selected to be the lowest state retention

voltage of a given process. Set by SPI bits SWxSTBY[4:0] and controlled by a Standby event (STANDBY logically and'd with

STANDBYSEC). Voltage transitions initiated by Standby are governed by the same DVS stepping that is programmed for

DVSx pin initiated transitions.

The following tables summarize the set point control and DVS time stepping applied to SW1 and SW2.

Table 49. DVS Control Logic Table for SW1 and SW2

SWx[4:0]

SWxDVS[4:0]

SWxSTBY[4:0]

Notes

60.

STANDBY is the logical anding of STANDBY and STANDBYSEC

STANDBY (60)

DVSx Pin

Set Point Selected by

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