ISL78310

9

FN7810.0

February 17, 2011

Applications Information

Input Voltage Requirements

ISL78310 is capable of delivering output voltages from 0.8V to

higher than the output voltage plus dropout at the maximum

rated current of the application if active filtering (PSRR) is

this family of LDOs allows applications to design for a level of

efficiency that can accommodate profiles smaller than the

TO220/263.

External Capacitor Requirements

GENERAL GUIDELINE

External capacitors are required for proper operation. Careful

attention must be paid to layout guidelines and selection of

capacitor type and value to ensure optimal performance.

OUTPUT CAPACITOR

The ISL78310 applies state-of-the-art internal compensation to

keep the selection of the output capacitor simple for the

range and load extremes are guaranteed for all capacitor types

and values assuming a minimum of 10µF X5R/X7R is used for

0.5cm. Additional capacitors of any value in ceramic, POSCAP,

alum/tantalum electrolytic types may be placed in parallel to

improve PSRR at higher frequencies and/or load transient AC

output voltage tolerances.

INPUT CAPACITOR

For proper operation, a minimum capacitance of 10µF X5R/X7R

is required at the input. This ceramic input capacitor must be

longer than 0.5cm.

A small phase boost capacitor, CPB, can be placed across the top

resistor in the feedback resistor divider network (Figure 13

below) in order to place a zero at:

This zero increases the crossover frequency of the LDO and

provides additional phase resulting in faster load transient

response.

It is also important to note that the LDO stability and load transient

are affected by the type of output capacitor used. For optimal

capacitors such as Aluminum Electrolytic or Tantalum are used.

values for different output voltage rails.

Thermal Fault Protection

In the event the die temperature exceeds typically +160°C, then

the output of the LDO shuts down until the die temperature cools

down to typically +130°C. The level of power, combined with the

thermal resistance of the package (+48°C/W for DFN),

determines whether the junction temperature exceeds the

thermal shutdown temperature specified in the “Electrical

Specifications” table on page 5 (see thermal packaging

guidelines).

(EQ. 1)

•

•

•

()

⁄

=

TABLE 1.

(V)

(kΩ)

(Ω)

(pF)

(µF)

5.0

2.61

287

100

10

3.3

2.61

464

100

10

2.5

2.61

649

82

10

1.8

2.61

1.0k

82

10

1.5*

2.61

1.3k

68

10

1.5

2.61

1.3k

150

22

1.2*

2.61

1.87k

120

22

1.2*

2.61

1.87k

270

47

1.0

2.61

2.61k

220

47

0.8

2.61

4.32k

220

47

*Either option could be used, depending on cost/performance

requirements.

ISL78310

EN

SS

PG

ADJ

FIGURE 13.