CYWUSB6953_10 datasheet(42/68 Pages) CYPRESS

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CYRF69103

Document #: 001-07611 Rev *F

Page 42 of 68

Table 19-11. P1.4–P1.6 Configuration (P14CR–P16CR) [0x11–0x13] [R/W]

Bit #

Field

SPI Use

Int Enable

Int Act Low

Reserved

High Sink

Open Drain

Pull up

Enable

Output

Enable

Read/Write

R/W

–R/W

R/W

Default

000

These registers control the operation of pins P1.4–P1.6, respectively.

The P1.4–P1.6 GPIO’s threshold is always set to TTL.

When the SPI hardware is enabled, pins that are configured as SPI Use have their output enable and output state controlled by

the SPI circuitry. When the SPI hardware is disabled or a pin has its SPI Use bit clear, the pin is controlled by the Output Enable

bit and the corresponding bit in the P1 data register.

Regardless of whether any pin is used as an SPI or GPIO pin the Int Enable, Int act Low, High Sink, Open Drain, and Pull up

Enable control the behavior of the pin.

The 50 mA sink drive capability is only available in the CY7C602xx. In the CY7C601xx, only 8 mA sink drive capability is available

on this pin regardless of the setting of the High Sink bit.

Bit 7

SPI Use

0 = Disable the SPI alternate function. The pin is used as a GPIO

1 = Enable the SPI function. The SPI circuitry controls the output of the pin

Bit 6

see Section 19.2.1

Bit 5

see Section 19.2.2

Bit 4

Reserved

Bit 3

see Section 19.2.4

Bit 2

see Section 19.2.5

Bit 1

see Section 19.2.6

Bit 0

see Section 19.2.7

Note For Comm Modes 01 or 10 (SPI Master or SPI Slave, see Table 19-15 on page 45)

When configured for SPI (SPI Use = 1 and Comm Modes [1:0] = SPI Master or SPI Slave mode), the input/output direction of

pins P1.3, P1.5, and P1.6 is set automatically by the SPI logic. However, pin P1.4's input/output direction is NOT automatically

set; it must be explicitly set by firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode,

pin P1.4 must be configured as an input.

Table 19-12. P1.7 Configuration (P17CR) [0x14] [R/W]

Bit #

Field

Reserved

Int Enable

Int Act Low

Reserved

High Sink

Open Drain

Pull up

Enable

Output

Enable

Read/Write

–

R/W

–

R/W

Default

00000000

This register controls the operation of pin P1.7.

50 mA sink drive capability is available. The P1.7 GPIO’s threshold is always set to TTL.

Bit 7

Reserved

Bit 6

see Section 19.2.1

Bit 5

see Section 19.2.2

Bit 4

Reserved

Bit 3

see Section 19.2.4

Bit 2

see Section 19.2.5

Bit 1

see Section 19.2.6

Bit 0

see Section 19.2.7

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