CYWUSB6953_10 datasheet(52/68 Pages) CYPRESS

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CYRF69103

Document #: 001-07611 Rev *F

Page 52 of 68

21.3.2 Interrupt Mask Registers

The Interrupt Mask Registers (INT_MSKx) are used to enable the individual interrupt sources’ ability to create pending interrupts.

There are four Interrupt Mask Registers (INT_MSK0, INT_MSK1, INT_MSK2, and INT_MSK3) that may be referred to in general as

INT_MSKx. If cleared, each bit in an INT_MSKx register prevents a posted interrupt from becoming a pending interrupt (input to the

priority encoder). However, an interrupt can still post even if its mask bit is zero. All INT_MSKx bits are independent of all other

INT_MSKx bits.

If an INT_MSKx bit is set, the interrupt source associated with that mask bit may generate an interrupt that becomes a pending

interrupt.

The Enable Software Interrupt (ENSWINT) bit in INT_MSK3[7] determines the way an individual bit value written to an INT_CLRx

register is interpreted. When is cleared, writing 1's to an INT_CLRx register has no effect. However, writing 0's to an INT_CLRx register,

when ENSWINT is cleared causes the corresponding interrupt to clear. If the ENSWINT bit is set, any 0's written to the INT_CLRx

registers are ignored. However, 1's written to an INT_CLRx register, while ENSWINT is set, cause an interrupt to post for the

corresponding interrupt.

Software interrupts can aid in debugging interrupt service routines by eliminating the need to create system level interactions that are

sometimes necessary to create a hardware-only interrupt.

Table 21-2. Interrupt Clear 0 (INT_CLR0) [0xDA] [R/W]

Bit #

Field

GPIO Port 1 Sleep Timer

INT1

GPIO Port 0 SPI Receive SPI Transmit

Reserved

POR/LVD

Read/Write

R/W

Default

When reading this register:

0 = There is no posted interrupt for the corresponding hardware.

1 = Posted interrupt for the corresponding hardware present.

Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits and to the ENSWINT

(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt.

The GPIO interrupts are edge-triggered.

Table 21-3. Interrupt Clear 1 (INT_CLR1) [0xDB] [R/W]

Bit #

Field

Reserved

Prog Interval

Timer

1 ms

Program-

mable

Interrupt

Reserved

Read/Write

R/W

–

––

–

Default

When reading this register:

0 = There is no posted interrupt for the corresponding hardware.

1 = Posted interrupt for the corresponding hardware present.

Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT.

Bit 7

Reserved

Table 21-4. Interrupt Clear 2 (INT_CLR2) [0xDC] [R/W]

Bit #

Field

Reserved

GPIO Port2

Reserved

INT2

16-bit

Counter

Wrap

Reserved

Read/Write

–

R/W

–R/W

R/W

Default

When reading this register:

0 = There is no posted interrupt for the corresponding hardware

1 = Posted interrupt for the corresponding hardware present.

Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT

(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt.

Bits 7,6,5,3,0]Reserved

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