MIC3003GFLTR datasheet(38/74 Pages) MICREL

38 / 74 page

Micrel, Inc.

MIC3003GFL

July 2010

M9999-072910-A

hbwhelp@micrel.com or (408) 955-1690

Serial Port Operation

The MIC3003 uses standard write byte, read byte, and

read word operations for communication with its host. It

also supports block write and block read transactions.

The write byte operation involves sending the devices

address (with the R/W bit low to signal a write operation),

followed by the address of the register to be operated

upon and the data byte. The read byte operation is a

composite write and read operation: the host first sends

the devices address followed by the register address, as

in a write operation. A new start bit must then be sent to

the MIC3003, followed by a repeat of the device address

with the R/W bit (LSB) set to the high (read) state. The

data to be read from the part may then be clocked out. A

read word is similar, but two successive data bytes are

clocked out rather than one. These protocols are shown

in Figures 21 to 24.

The MIC3003 will respond to up to four sequential device

addresses depending upon whether it is in OEM or User

mode. A match between one of the MIC3003’s addresses

and the address specified in the serial bit stream must be

made to initiate communication. The MIC3003 responds

to device addresses A0h and A2h in User Mode; it also

responds to A4h and A6h in OEM Mode (assuming the

base address is A0h).

Block Writes

To increase the speed of block writes, the MIC3003 allows

up to eight consecutive bytes to be written before the

internal memory update begins.

The block write sequence begins just like a write byte

operation with the host sending the device address, R/W bit

low, register address, etc. After the first data byte is sent

the host will receive an acknowledge. Up to seven more

bytes can be sent in sequence. The MIC3003 will

acknowledge each one and increment its internal address

sent, the host issues a STOP. The MIC3003’s internal write

process then begins.

Block writes of up to eight bytes can begin and end at any

byte address without restriction. Block writes that increment

over register address FFh will simply “wrap around” and

continue at address 00h within the same device address

space.

To accelerate calibration and testing, NVRAM write cycles

can be disabled completely by setting the WRINH bit in

OEMCAL0. Writes to registers that do not have NVRAM

backup, will not incur write-cycle delays when writes are

inhibited. Write operations on registers that exist only in

NVRAM will still incur write cycle delays.

Figure 21. Write Byte Protocol

Figure 22. Read Byte Protocol

Figure 23. Read_Word Protocol

MIC3003GFLTR 데이터시트(PDF) 38 Page - Micrel Semiconductor

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