PIC16F1847 datasheet(21/408 Pages) MICROCHIP

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 2011 Microchip Technology Inc.

Preliminary

DS41453B-page 21

PIC16(L)F1847

3.2

Data Memory Organization

The data memory is partitioned in 32 memory banks

with 128 bytes in a bank. Each bank consists of

(Figure 3-2):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number

into the Bank Select Register (BSR). Unimplemented

memory will read as ‘0’. All data memory can be

accessed either directly (via instructions that use the

file registers) or indirectly via the two File Select

Registers

(FSR).

See

Section 3.5

“Indirect

Addressing”

for more information.

3.2.1

CORE REGISTERS

The core registers contain the registers that directly

affect the basic operation of the PIC16F/LF1847. These

registers are listed below:

• INDF0

• INDF1

•PCL

•STATUS

•FSR0 Low

• FSR0 High

•FSR1 Low

• FSR1 High

• BSR

•WREG

•PCLATH

•INTCON

3.2.1.1

STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF

and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section 29.0

“Instruction Set Summary”

Note:

The core registers are the first 12

addresses of every data memory bank.

Note 1:

The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in

subtraction.

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