MPC5644B datasheet(82/114 Pages) FREESCALE

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MPC5646C Microcontroller Data Sheet, Rev. 3

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

4.18

Fast Ethernet Controller

MII signals use CMOS signal levels compatible with devices operating at 3.3 V. Signals are not TTL compatible. They follow

the CMOS electrical characteristics.

4.18.1

MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency

requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency in 2:1 mode and two times

the RX_CLK frequency in 1:1 mode.

3 PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from V

DD_HV_B domain hence VDD_HV_ADC1

should be within ±100 mV of VDD_HV_B when these channels are used for ADC_1.

4 VDD_HV_ADC1 can operate at 5V condition while V

DD_HV_B can operate at 3.3V provided that ADC_1 channels

coming from VDD_HV_B domain are limited in max swing as VDD_HV_B.

5 V

AINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the

conversion will be clamped respectively to 0x000 or 0xFFF.

6 During the sample time the input capacitance C

S can be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the

end of the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values

for the sample clock tADC1_S depend on programming.

7 Conversion time = Bit evaluation time + Sampling time + 1 Clock cycle delay.

8 Refer to ADC conversion table for detailed calculations.

9 Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a

combination of Offset, Gain and Integral Linearity errors.

Table 44. MII Receive Signal Timing

Spec

Characteristic

Min

Max

Unit

RXD[3:0], RX_DV,

RX_ER to RX_CLK

setup

5—

RX_CLK to

RXD[3:0], RX_DV,

RX_ER hold

5—

RX_CLK pulse width

high

35%

65%

RX_CLK period

RX_CLK pulse width

low

35%

65%

RX_CLK period

MPC5644B 데이터시트(PDF) 82 Page - Freescale Semiconductor, Inc

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