AD9643 datasheet(9/36 Pages) AD

부품명	AD9643

상세설명	14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

PDF	36 Pages

Scroll/Zoom	100%

제조업체	AD [Analog Devices]

홈페이지	http://www.analog.com

Logo

9 / 36 page

AD9643

Rev. A | Page 9 of 36

TIMING SPECIFICATIONS

Table 5.

Parameter

Conditions

Min

Typ

Max

Unit

SYNC TIMING REQUIREMENTS

tSSYNC

SYNC to the rising edge of CLK setup time

0.3

tHSYNC

SYNC to the rising edge of CLK hold time

0.4

SPI TIMING REQUIREMENTS

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

Minimum period that SCLK should be in a logic high state

tLOW

Minimum period that SCLK should be in a logic low state

tEN_SDIO

Time required for the SDIO pin to switch from an input to an output

relative to the SCLK falling edge

tDIS_SDIO

Time required for the SDIO pin to switch from an output to an input

relative to the SCLK rising edge

AD9643 데이터시트(PDF) 9 Page - Analog Devices