AD9643 datasheet(12/36 Pages) AD

12 / 36 page

AD9643

Rev. A | Page 12 of 36

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CLK+

CLK–

SYNC

DNC

(LSB) D0–

(LSB) D0+

DRVDD

D1–

D1+

D2–

D2+

D3–

D3+

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE

PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART.

THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND

FOR PROPER OPERATION.

PDWN

OEB

CSB

SCLK

SDIO

OR+

OR–

D13+ (MSB)

D13– (MSB)

D12+

D12–

DRVDD

D11+

D11–

D10+

D10–

AD9643

PARALLEL LVDS

TOP VIEW

(Not to Scale)

PIN 1

INDICATOR

Figure 4. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)

Table 8. Pin Function Descriptions for Interleaved Parallel LVDS Mode

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

10, 19, 28, 37

DRVDD

Supply

Digital Output Driver Supply (1.8 V Nominal).

49, 50, 53, 54, 59, 60, 63, 64

AVDD

Supply

Analog Power Supply (1.8 V Nominal).

4, 5, 6, 7, 55, 56, 58

DNC

Do Not Connect. Do not connect to this pin.

AGND,

Exposed Paddle

Ground

Analog Ground. The exposed thermal paddle on the bottom of the

package provides the analog ground for the part. This exposed

paddle must be connected to ground for proper operation.

ADC Analog

VIN+A

Input

Differential Analog Input Pin (+) for Channel A.

VIN−A

Input

Differential Analog Input Pin (−) for Channel A.

VIN+B

Input

Differential Analog Input Pin (+) for Channel B.

VIN−B

Input

Differential Analog Input Pin (−) for Channel B.

VCM

Output

Common-Mode Level Bias Output for Analog Inputs. This pin

should be decoupled to ground using a 0.1 μF capacitor.

CLK+

Input

ADC Clock Input—True.

CLK−

Input

ADC Clock Input—Complement.

Digital Input

SYNC

Input

Digital Synchronization Pin. Slave mode only.

Digital Outputs

D0+ (LSB)

Output

Channel A/Channel B LVDS Output Data 0—True.

D0− (LSB)

Output

Channel A/Channel B LVDS Output Data 0—Complement.

D1+

Output

Channel A/Channel B LVDS Output Data 1—True.

D1−

Output

Channel A/Channel B LVDS Output Data 1—Complement.

D2+

Output

Channel A/Channel B LVDS Output Data 2—True.

D2−

Output

Channel A/Channel B LVDS Output Data 2—Complement.

D3+

Output

Channel A/Channel B LVDS Output Data 3—True.

D3−

Output

Channel A/Channel B LVDS Output Data 3—Complement.

D4+

Output

Channel A/Channel B LVDS Output Data 4—True.

AD9643 데이터시트(PDF) 12 Page - Analog Devices

AD9643 데이터시트(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

데이터시트 다운로드

링크 URL