SC1406

© 1999 SEMTECH CORP.

652 MITCHELL ROAD

NEWBURY PARK CA 91320

PORTABLE PENTIUM

POWER SUPPLY CONTROLLER

PRELIMINARY - August 27, 1999

8

Pentium is a registered trademark of Intel Corporation

FUNCTIONAL DESCRIPTION

SUPPLY

The chip is optimized to operate from a 3.3V + 5% rail

but is also designed to work up to 6V maximum supply

voltage. If V

the quiescent current will increase somewhat and

slight degradation of line regulation is expected.

UNDER VOLTAGE LOCK-OUT CIRCUIT

The under voltage lockout circuit consists of two com-

parators, the low battery and low V

age) comparators. The output of the comparator

gated with the Enable signal turns on or off the inter-

nal bias, enables or disables the CO output, and

initiates or resets the soft start timers.

POWER GOOD GENERATOR

If the chip is enabled but not in UVLO condition, and

the core voltage gets within +10% of the VID pro-

grammed value, then a high level Power Good signal

is generated on the PWRGD pin to trigger the CPU

power up sequence. If the chip is either disabled or

enabled in UVLO condition, then PWRGD stays low.

This condition is satisfied by the presence of an inter-

nal 100k

Ω pull-down resistor connected from PWRGD

to ground.

During soft start, PWRGD stays low independently

from the status of Vcore voltage. During this time,

PWRGD status is “don’t care”.

BAND GAP REFERENCE

A better than +1% precision band gap reference acts

as the internal reference voltage standard of the chip,

which all critical biasing voltages and currents are de-

rived from.

CORE CONVERTER CONTROLLER

Precision VID DAC Reference

The 5-bit digital to analog converter (DAC) serves as

the programmable reference source of the core com-

parator. Programming is accomplished by CMOS logic

level VID code applied to the DAC inputs. The VID

code vs. the DAC output is shown in the Output Volt-

age Table. The accuracy of the VID DAC is main-

tained on the same level as the band gap reference.

There is a 10µA pull-up current on each DAC input

while EN is high.

Core Comparator

This is an ultra-fast hysteretic comparator with a typi-

cal propagation delay of approximately 20ns at a

20mV overdrive. Its hysteresis is determined by the

resistance ratio of two external resistors, R

and the high accuracy internal reference voltage, V

This chip can be used in standard hysteretic mode

controller configuration and in DSPS (Dynamic Set

Point Switching) hysteretic controller scheme.

In standard hysteretic controller configuration, the

core comparator compares the output voltage of the

core converter, V

DAC voltage, V

V

The core voltage ramps up and down between the two

thresholds determined by the hysteresis of the com-

parator:

V

V

In DSPS hysteretic controller configuration, the

core comparator compares the core voltage, V

not to the DAC voltage, V

voltage less than the DAC voltage by a DSPS voltage,

V

The DSPS voltage is a function of the load current. It

is generated from the current sense voltage, V

developed across a sense resistor, R

serted in series with the main buck inductor and also

used for current sensing for the cycle-by-cycle current

limiting. The sense voltage is scaled up by the DSPS

gain, A

external resistors, R

V

R

OH

R

HYS

V

V

) • R

R

DAC

R

CORE