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SC1406TS 데이터시트(PDF) 10 Page - Semtech Corporation |
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SC1406TS 데이터시트(HTML) 10 Page - Semtech Corporation |
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10 / 11 page ![]() SC1406 © 1999 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PORTABLE PENTIUM ® II & III POWER SUPPLY CONTROLLER PRELIMINARY - August 27, 1999 10 Pentium is a registered trademark of Intel Corporation Core Converter Soft Start Timer The main purpose of this block is to control the ramp- up time of the core voltage in order to reduce the ini- tial inrush current on the core input voltage (battery) rail. The soft start circuit consists of an internal cur- rent source, external soft start timing capacitor, inter- nal switch across the capacitor, and a comparator monitoring the capacitor voltage. LINEAR REGULATOR CONTROLLER 1.5V Linear Regulator This block is a linear regulator controller, which drives an external PNP bipolar transistor as a pass element. The linear regulator is capable of delivering 500mA steady state DC current and should support transient current of 1A, assuming the output filtering capacitor is properly selected to provide enough charge for the duration of the load transient. 2.5V Linear Regulator This block is a low drop-out (LDO) linear regulator controller, which drives an external PNP bipolar tran- sistor as a pass element. The LDO linear regulator is capable of delivering 100mA steady DC current and should support transient current of 100mA, assuming the output filtering capacitor is properly selected to provide enough charge for the duration of the load transient. Linear Regulator Soft Start Timer A soft start timer circuit of the linear regulators is simi- lar to that of the core converter, and is used to control the ramp up time of the linear regulator output volt- ages. For maximum flexibility in controlling the start up sequence, the soft start function of the linear regu- lators is separated from that of the core converter. VOLTAGE CLAMP The level translator converts an input voltage swing on the IO rail, into a voltage swing on the CLK or VCC rail depending on where the open drain output of the translator is tied to through an external pull-up resistor. The level translator has to track the input in phase, and must be able to switch in 5ns (typical) following an input threshold intercept. APPLICATION INFORMATION Power on/off Sequence |
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