TMS570LS3137 datasheet(68/159 Pages) TI

68 / 159 page

TMS570LS3137

SPNS162.

– SEPTEMBER 2011

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An additional use of this module is to measure the frequency of a selectable clock source, using the input

clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a

fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width

pulse (1 cycle) after a pre-programmed number of pulses. This pulse sets as an error signal if counter 1

does not reach 0 within the counting window generated by counter 0.

4.7.3.1

Features

•

Takes two different clock sources as input to two independent counter blocks.

•

One of the clock sources is the known-good, or reference clock; the second clock source is the "clock

under test."

•

Each counter block is programmable with initial, or seed values.

•

The counter blocks start counting down from their seed values at the same time; a mismatch from the

expected frequency for the clock under test generates an error signal which is used to interrupt the

CPU.

4.7.3.2

Mapping of DCC Clock Source Inputs

Table 4-16. DCC1 Counter 0 Clock Sources

CLOCK SOURCE [3:0]

CLOCK NAME

others

oscillator (OSCIN)

0x5

high frequency LPO

0xA

test clock (TCK)

Table 4-17. DCC1 Counter 1 Clock Sources

KEY [3:0]

CLOCK SOURCE [3:0]

CLOCK NAME

others

N2HET1[31]

0x0

Main PLL free-running clock output

0x1

PLL #2 free-running clock output

0x2

low frequency LPO

0xA

0x3

high frequency LPO

0x4

flash HD pump oscillator

0x5

EXTCLKIN1

0x6

EXTCLKIN2

0x7

ring oscillator

0x8 - 0xF

VCLK

Table 4-18. DCC2 Counter 0 Clock Sources

CLOCK SOURCE [3:0]

CLOCK NAME

others

oscillator (OSCIN)

0xA

test clock (TCK)

Table 4-19. DCC2 Counter 1 Clock Sources

KEY [3:0]

CLOCK SOURCE [3:0]

CLOCK NAME

others

N2HET2[0]

0xA

00x0 - 0x7

Reserved

0x8 - 0xF

VCLK

System Information and Electrical Specifications

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