L3G4200D datasheet(31/42 Pages) STMICROELECTRONICS

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L3G4200D

Doc ID 17116 Rev 3

31/42

7.4

CTRL_REG3 (22h)

Table 26.

High pass filter mode configuration

HPM1

HPM0

High Pass filter Mode

Normal mode (reset reading HP_RESET_FILTER)

Reference signal for filtering

Normal mode

Autoreset on interrupt event

Table 27.

High pass filter cut off frecuency configuration [Hz]

HPCF3

ODR= 100 Hz

ODR= 200 Hz

ODR= 400 Hz

ODR= 800 Hz

0000

153056

0001

0010

0011

0100

0.5

0101

0.2

0.5

0110

0.1

0.2

0.5

0111

0.05

0.1

0.2

0.5

1000

0.02

0.05

0.1

0.2

1001

0.01

0.02

0.05

0.1

Table 28.

CTRL_REG1 register

I1_Int1

I1_Boot

H_Lactive

PP_OD

I2_DRDY

I2_WTM

I2_ORun

I2_Empty

Table 29.

CTRL_REG3 description

I1_Int1

Interrupt enable on INT1 pin. Default value 0. (0: Disable; 1: Enable)

I1_Boot

Boot status available on INT1. Default value 0. (0: Disable; 1: Enable)

H_Lactive

Interrupt active configuration on INT1. Default value 0. (0: High; 1:Low)

PP_OD

Push- Pull / Open drain. Default value: 0. (0: Push- Pull; 1: Open drain)

I2_DRDY

Date Ready on DRDY/INT2. Default value 0. (0: Disable; 1: Enable)

I2_WTM

FIFO Watermark interrupt on DRDY/INT2. Default value: 0. (0: Disable; 1: Enable)

I2_ORun

FIFO Overrun interrupt on DRDY/INT2 Default value: 0. (0: Disable; 1: Enable)

I2_Empty

FIFO Empty interrupt on DRDY/INT2. Default value: 0. (0: Disable; 1: Enable)

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