TJ2995DP datasheet(5/9 Pages) HTC

5 / 9 page

DDR Termination Regulator

TJ2995

Oct. 2009 - Rev. 1.1

5/9

HTC

DESCRIPTION

The TJ2995 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2

and SSTL-3. The TJ2995 is capable of sinking and sourcing current at the output VTT, regulating the

voltage to equal VDDQ / 2. A buffered reference voltage that also tracks VDDQ / 2 is generated on the VREF

pin for providing a global reference to the DDR-SDRAM and Northbridge Chipset. VTT is designed to

track the VREF voltage with a tight tolerance over the entire current range while preventing shoot through

on the output stage.

Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission

across the memory bus. This termination scheme is essential to prevent data error from signal reflections

while transmitting at high frequencies encountered with DDR RAM. The most common form of termination

is Class II single parallel termination. This involves using one RS series resistor from the chipset to the

memory and one RT termination resistor. This implementation can be seen below in Figure 1.

FIGURE 1. SSTL-Termination Scheme

PIN DESCRIPTION

AVIN AND PVIN

AVIN and PVIN are the input supply pins for the TJ2995. AVIN is used to supply all the internal control

circuitry for the two op-amps and the output stage of VREF. PVIN is used exclusively to provide the rail

voltage for the output stage on the power operational amplifier used to create VTT. For SSTL-2

applications AVIN and PVIN pins should be connected directly and tied to the 2.5V rail for optimal

performance. This eliminates the need for bypassing the two supply pins separately.

VDDQ

VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference

voltage is generated from a resistor divider of two internal 50㏀ resistors. This guarantees that VTT will

track VDDQ / 2 precisely. The optimal implementation of VDDQ is as a remote sense. This can be

achieved by connecting VDDQ directly to the 2.5V rail at the DIMM instead of AVIN and PVIN. This ensures

that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from

the power lines. For SSTL-2 applications VDDQ will be a 2.5V signal, which will create a 1.25V

termination voltage at VTT (See Electrical Characteristics Table for exact values of VTT over

temperature).

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