TJ2995DP datasheet(8/9 Pages) HTC

8 / 9 page

DDR Termination Regulator

TJ2995

Oct. 2009 - Rev. 1.1

8/9

HTC

TYPICAL APPLICATION INFORMATION

The typical application circuit used for SSTL-2 termination schemes with DDR-SDRAM can be seen in

Figure 2.

FIGURE 2. SSTL-2 Implementation

For SSTL-3 and other applications, it may be desirable to change internal reference voltage scaling

from the VDDQ / 2. An external resistor in series with the VDDQ pin can be used to lower the reference

voltage. Internally two 50 kΩ resistors set the output VTT to be equal to VDDQ / 2. The addition of a 11.1

kΩ external resistor will change the internal reference voltage causing the two outputs to track VDDQ * 0.45.

An implementation of this circuit can be seen in Figure 3.

FIGURE 3. SSTL-3 Implementation

Another application that is sometimes required is to increase the VTT output voltage from the scaling

factor of VDDQ * 0.5. This can be accomplished independently of VREF by using a resistor divider network

between VTT, VSENSE and Ground. An example of this circuit can be seen in Figure 4.

FIGURE 4. Increased VTT from the Scaling Factor

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