LIS331HH datasheet(25/37 Pages) STMICROELECTRONICS

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LIS331HH

Doc ID 16366 Rev 1

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7.2

CTRL_REG2 (21h)

BOOT bit is used to refresh the content of internal registers stored in the flash memory

block. At the device power up the content of the flash memory block is transferred to the

internal registers related to trimming functions to permit a good behavior of the device itself.

If for any reason the content of trimming registers was changed it is sufficient to use this bit

to restore correct values. When BOOT bit is set to ‘1’ the content of internal flash is copied

Low-power

Table 19.

Normal-mode output data rate configurations and low-pass cut-off

frequencies

DR1

DR0

Output Data Rate [Hz]

ODR

Low-pass filter cut-off

frequency [Hz]

100

400

292

1000

780

Table 18.

Power mode and low-power output data rate configurations (continued)

PM2

PM1

PM0

Power mode selection

Output data rate [Hz]

ODRLP

Table 20.

CTRL_REG2 register

BOOT

HPM1

HPM0

FDS

HPen2

HPen1

HPCF1

HPCF0

Table 21.

CTRL_REG2 description

BOOT

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

HPM1, HPM0

High pass filter mode selection. Default value: 00

(00: normal mode; Others: refer to

Table 22)

FDS

Filtered data selection. Default value: 0

(0: internal filter bypassed; 1: data from internal filter sent to output register)

HPen2

High pass filter enabled for interrupt 2 source. Default value: 0

(0: filter bypassed; 1: filter enabled)

HPen1

High pass filter enabled for interrupt 1 source. Default value: 0

(0: filter bypassed; 1: filter enabled)

HPCF1,

HPCF0

High pass filter cut-off frequency configuration. Default value: 00

(00: HPc=8; 01: HPc=16; 10: HPc=32; 11: HPc=64)

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