STTS2002_11 datasheet(34/52 Pages) STMICROELECTRONICS

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SPD EEPROM operation

STTS2002

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Doc ID 15389 Rev 5

5.5

Write operations

Following a start condition the bus master sends a device select code with the RW bit reset

to 0. The device acknowledges this, as shown in Figure 12, and waits for an address byte.

The device responds to the address byte with an acknowledge bit, and then waits for the

data byte.

When the bus master generates a stop condition immediately after the ack bit (in the “10th

bit” time slot), either at the end of a byte write or a page write, the internal memory write

cycle is triggered. A stop condition at any other time slot does not trigger the internal write

cycle.

During the internal write cycle, serial data (SDA) and serial clock (SCL) are ignored, and the

device does not respond to any requests.

5.5.1

Byte write

After the device select code and the address byte, the bus master sends one data byte. If

the addressed location is hardware write-protected, the device replies to the data byte with

NoAck, and the location is not modified. If, instead, the addressed location is not write-

protected, the device replies with Ack. The bus master terminates the transfer by generating

a stop condition, as shown in Figure 12.

5.5.2

Page write

The page write mode allows up to 16 bytes to be written in a single write cycle, provided that

they are all located in the same page in the memory: that is, the most significant memory

address bits are the same. If more bytes are sent than will fit up to the end of the page, a

condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become

overwritten in an implementation dependent way.

The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the

device. After each byte is transferred, the internal byte address counter (the 4 least

significant address bits only) is incremented. The transfer is terminated by the bus master

generating a stop condition.

Figure 12.

Write mode sequences in a non write-protected area of SPD

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

AI01941

DATA IN N

ACK

R/W

ACK

R/W

ACK

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