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ADL5240ACPZ-R7 데이터시트(PDF) 20 Page - Analog Devices |
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ADL5240ACPZ-R7 데이터시트(HTML) 20 Page - Analog Devices |
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20 / 24 page ![]() ADL5240 Rev. 0 | Page 20 of 24 NC VDD NC NC NC DSAOUT NC NC NC NC VDD DSAIN ADL5240 NC NC NC NC SERIAL PARALLEL INTERFACE 68pF 1.2nF 470nH VDD 100pF VDD 0.1µF RFOUT 0.1µF RFIN 1µF VCC C1 C3 C4 C5 C6 C7 C2 100pF L1 1 2 3 4 5 6 7 8 910 16 15 14 13 12 11 24 23 22 21 20 19 18 17 32 31 25 26 27 28 29 30 Figure 37. AMP-DSA Loop Configuration THERMAL CONSIDERATIONS The ADL5240 is packaged in a thermally efficient, 5 mm × 5 mm, 32-lead LFCSP. The thermal resistance from junction to air (θJA) is 36.8oC/W. The thermal resistance for the product was extracted assuming a standard 4-layer JEDEC board with 25 conductive, epoxy filled thermal vias. The thermal resistance from junction to case (θJC) is 6.9oC/W, where case is the exposed pad of the lead frame package. The ADL5240 consumes approximately 93 mA with a 5 V supply voltage. Even though the part dissipates less than 0.5 W, for the best thermal performance, it is recommended to add as many thermal vias as possible under the exposed pad of the LFCSP. The thermal resistance values given in this section assume a minimum of 25 thermal vias arranged in a 5 × 5 array with a diameter of 13 mils and a pitch of 25 mils. Figure 38 shows a close-up of the thermal via distribution under the exposed pad. Figure 38. Exposed Pad with Thermal Via Distribution |
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