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AFS090 데이터시트(PDF) 115 Page - Microsemi Corporation |
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AFS090 데이터시트(HTML) 115 Page - Microsemi Corporation |
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115 / 334 page ![]() Fusion Family of Mixed Signal FPGAs R e visio n 2 2 - 99 ADC Description The Fusion ADC is a 12-bit SAR ADC. It offers a wide variety of features for different use models. Figure 2-78 shows a block diagram of the Fusion ADC. • Configurable resolution: 8-bit, 10-bit, and 12-bit mode • DNL: 0.6 LSB for 10-bit mode • INL: 0.4 LSB for 10-bit mode • No missing code • Internal VAREF = 2.56 V • Maximum Sample Rate = 600 Ksps • Power-up calibration and dynamic calibration after every sample to compensate for temperature drift over time ADC Theory of Operation An analog-to-digital converter is used to capture discrete samples of a continuous analog voltage and provide a discrete binary representation of the signal. Analog-to-digital converters are generally characterized in three ways: • Input voltage range • Resolution • Bandwidth or conversion rate The input voltage range of an ADC is determined by its reference voltage (VREF). Fusion devices include an internal 2.56 V reference, or the user can supply an external reference of up to 3.3 V. The following examples use the internal 2.56 V reference, so the full-scale input range of the ADC is 0 to 2.56 V. The resolution (LSB) of the ADC is a function of the number of binary bits in the converter. The ADC approximates the value of the input voltage using 2n steps, where n is the number of bits in the converter. Each step therefore represents VREF÷ 2n volts. In the case of the Fusion ADC configured for 12-bit operation, the LSB is 2.56 V / 4096 = 0.625 mV. Finally, bandwidth is an indication of the maximum number of conversions the ADC can perform each second. The bandwidth of an ADC is constrained by its architecture and several key performance characteristics. Figure 2-78 • ADC Simplified Block Diagram TVC SYSCLK ADCCLK Signals from Analog Quads CHNUMBER SAR ADC STC MODE RESULT DATAVALID BUSY STATUS SAMPLE CALIBRATE VAREF Analog MUX 32 12 |
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