Data Output

by Transmitter

Data Output

by Receiver

SCL From

Master

Start

Condition

Clock Pulse for

Acknowledgment

ACK

NACK

1

2

8

9

SCL

ST

SDA

0

1

0

0

1

0

1

0

A

0

0

0

0

0

0

1

0

A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A SP

Start

Slave Address

W/R

Ack. from slave

Sub Address

Ack

from

slave

Auto-Inc.

Register Address

(Control Reg)

Ack

from

slave

Ack

from

slave

Stop

Data to Control

Register

Data to Control Register

Date Byte

Date Byte

SDA

ST

0

1

0

0

1

0

1

0

A

1

0

0

0

1

0

0

0

A

D7 D6 D5 D4 D3 D2 D1 D0

A

D7 D6 D5 D4 D3 D2 D1 D0

A

Start

Slave Address

W/R

Ack. from slave

Sub Address

Ack

from

slave

Auto-Inc.

Ack

from

slave

Data to Timing Set 1

Register

Data to Timing Set 2

Register

Date Byte

Date Byte

Register Address

(Timing Set 1 Reg)

TSU6111A

www.ti.com

SCDS331

– FEBRUARY 2012

Writes

Data is transmitted to the TSU6111A by sending the device slave address and setting the LSB to a logic 0 (see

Figure 5 for device address). The command byte is sent after the address and determines which register

receives the data that follows the command byte. The next byte is written to the specified register on the rising

edge of the ACK clock pulse.

Figure 5. Repeated Data Write to a Single Register

Figure 6. Burst Data Write to Multiple Registers

Reads

The bus master must first send the TSU6111A slave address with the LSB set to logic 0. The command byte is

sent after the address and determines which register is accessed. After a restart, the device slave address is

sent again but, this time, the LSB is set to logic 1. Data from the register defined by the command byte then is

sent by the TSU6111A. Data is clocked into the SDA output shift register on the rising edge of the ACK clock

pulse (See Figure 7).

Copyright

© 2012, Texas Instruments Incorporated

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