SLx 24C01/02/P

Semiconductor Group

7

1998-07-27

3

I

The SLx 24C01/02/P devices support a master/slave bidirectional bus oriented protocol

in which the EEPROM always takes the role of a slave.

Figure 3

Bus Configuration

Master

Device that initiates the transfer of data and provides the clock for both

transmit and receive operations.

Slave

Device addressed by the master, capable of receiving and transmitting

data.

Transmitter The device with the SDA as output is defined as the transmitter. Due to

the open drain characteristic of the SDA output the device applying a low

level wins.

Receiver

The device with the SDA as input is defined as the receiver.

Slave 1

Slave 2

Slave 3

Slave 4

Slave 8

Slave 5

Slave 6

Slave 7

Master

CC

V

IES02183

SCL

SDA