SLx 24C01/02/P

Semiconductor Group

20

1998-07-27

7.2

Protection Bit Write and Erase

For writing or erasing a protection bit, the data of the respective page have to be known

by the master. The data of the page are not affected by the write or erase procedure of

the protection bit. The I

figure 16 for protection bit erase.

Figure 15

Sequence for Protection Bit Write

Figure 16

Sequence for Protection Bit Erase

The first command byte CSW followed by the control byte EEA addresses the page to

be protected. The second command byte CSW (identical content of first CSW) is

followed by the control byte CTW = 01

bit erase. Depending on CTx, the addressed protection bit will be either written or

erased.

P

T

P

O

S

Bus Activity

Master

SDA Line

Bus Activity

EEPROM

IED02142

S

R

T

A

T

S

Command

Byte

CSW

EEPROM

Address

EEA n

Byte n

Data

Byte n+1

Data

Byte n+7

Data

C

K

A

1

0

0

0

0

0

00

...

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

R

T

A

T

S

S

Command

Byte

CSW

Control

Byte

CTW

P

T

P

O

S

Bus Activity

Master

SDA Line

Bus Activity

EEPROM

IED02143

S

R

T

A

T

S

Command

Byte

CSW

EEPROM

Address

EEA n

Byte n

Data

Byte n+1

Data

Byte n+7

Data

C

K

A

1

1

0

0

0

0

00

...

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

A

R

T

A

T

S

S

Command

Byte

CSW

Control

Byte

CTE