MPC5643L datasheet(19/136 Pages) FREESCALE

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Introduction

MPC5643L Microcontroller Data Sheet, Rev. 8.1

Freescale Semiconductor

— A/D Channels: 9 external, 3 internal and 4 shared with other A/D (total 16 channels)

— One channel dedicated to each T-sensor to enable temperature reading during application

— Separated reference for each ADC

— Shared analog supply voltage for both ADCs

— One sample and hold unit per ADC

— Adjustable sampling and conversion time

Digital part:

•

4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in

the appropriate ADC result location

•

2 modes of operation: CPU Mode or CTU Mode

•

CPU mode features

— Register based interface with the CPU: one result register per channel

— ADC state machine managing three request flows: regular command, hardware injected command, software

injected command

— Selectable priority between software and hardware injected commands

— 4 analog watchdogs comparing ADC results against predefined levels (low, high, range)

— DMA compatible interface

•

CTU mode features

— Triggered mode only

— 4 independent result queues (1

 16 entries, 2  8 entries, 1  4 entries)

— Result alignment circuitry (left justified; right justified)

— 32-bit read mode allows to have channel ID on one of the 16-bit parts

— DMA compatible interfaces

•

Built-in self-test features triggered by software

1.5.34

Cross Triggering Unit (CTU)

The ADC cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without

CPU load during the PWM period and with minimized CPU load for dynamic configuration.

The CTU implements the following features:

•

Cross triggering between ADC, FlexPWM, eTimer, and external pins

•

Double buffered trigger generation unit with as many as 8 independent triggers generated from external triggers

•

Maximum operating frequency less than or equal to 120 MHz

•

Trigger generation unit configurable in sequential mode or in triggered mode

•

Trigger delay unit to compensate the delay of external low pass filter

•

Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation

•

Double buffered ADC command list pointers to minimize ADC-trigger unit update

•

Double buffered ADC conversion command list with as many as 24 ADC commands

•

Each trigger capable of generating consecutive commands

•

ADC conversion command allows control of ADC channel from each ADC, single or synchronous sampling,

independent result queue selection

•

DMA support with safety features

1.5.35

Cyclic Redundancy Checker (CRC) Unit

The CRC module is a configurable multiple data flow unit to compute CRC signatures on data written to its input register.

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