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SL74HC161 데이터시트(PDF) 5 Page - System Logic Semiconductor

부품명 SL74HC161
상세설명  Presettable Counters
PDF  9 Pages
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제조업체  SLS [System Logic Semiconductor]
홈페이지  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL74HC161 데이터시트(HTML) 5 Page - System Logic Semiconductor

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SL74HC161
System Logic
Semiconductor
SLS
TIMING REQUIREMENTS (C
L=50pF,Input t r=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25
°C to
-55
°C
≤85°C
≤125°C
Unit
tSU
Minimum Setup Time, Preset Data Inputs to Clock
(Figure 4)
2.0
4.5
6.0
40
15
12
60
20
18
80
30
20
ns
tSU
Minimum Setup Time, Load to Clock
(Figure 4)
2.0
4.5
6.0
60
15
12
75
20
18
90
30
20
ns
tSU
Minimum Setup Time, Enable T or Enable P to
Clock (Figure 5)
2.0
4.5
6.0
80
20
17
95
25
23
110
35
25
ns
th
Minimum Hold Time, Clock to Load or Preset Data
Inputs (Figure 4)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
th
Minimum Hold Time, Clock to Enable T or Enable
P (Figure 5)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
trec
Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
80
15
12
95
20
17
110
26
23
ns
trec
Minimum Recovery Time, Load Inactive to Clock
(Figure 4)
2.0
4.5
6.0
80
15
12
95
20
17
110
26
23
ns
tw
Minimum Pulse Width, Clock (Figure 1)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tw
Minimum Pulse Width, Reset (Figure 2)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns



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