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CDCP1803MRGETEP 데이터시트(PDF) 5 Page - Texas Instruments

부품명 CDCP1803MRGETEP
상세설명  1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER
PDF  24 Pages
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CDCP1803MRGETEP 데이터시트(HTML) 5 Page - Texas Instruments

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CDCP1803-EP
www.ti.com........................................................................................................................................................................................... SCAS864 – DECEMBER 2008
Table 1. Selection Mode Table
LVPECL(1)
MODE
EN
S2
S1
S0
Y0
Y1
Y2
0
0
x
x
x
Off (high-z)
1
1
0
0
0
÷ 1
÷ 1
÷ 1
2
1
0
0
VDD/2
÷ 1
Off (high-z)
Off (high-z)
3
1
0
0
1
÷ 1
÷ 1
Off (high-z)
4
1
0
VDD/2
0
÷ 1
÷ 2
Off (high-z)
5
1
0
VDD/2
VDD/2
÷ 1
÷ 4
Off (high-z)
6
1
0
VDD/2
1
÷ 1
÷ 8
Off (high-z)
7
1
0
1
0
÷ 1
Off (high-z)
÷ 1
8
1
0
1
1
÷ 1
÷ 2
÷ 1
9
1
VDD/2
0
0
÷ 1
÷ 4
÷ 1
10
1
VDD/2
0
VDD/2
÷ 1
÷ 8
÷ 1
11
1
VDD/2
0
1
÷ 1
Off (high-z)
÷ 2
12
1
VDD/2
VDD/2
0
÷ 1
÷ 1
÷ 2
13
1
VDD/2
VDD/2
VDD/2
÷ 1
÷ 2
÷ 2
14
1
VDD/2
VDD/2
1
÷ 1
÷ 4
÷ 2
15
1
VDD/2
1
0
÷ 1
÷ 8
÷ 2
16
1
VDD/2
1
VDD/2
÷ 1
Off (high-z)
÷ 4
17
1
VDD/2
1
1
÷ 1
÷ 1
÷ 4
18
1
1
0
0
÷ 1
÷ 2
÷ 4
19
1
1
0
VDD/2
÷ 1
÷ 4
÷ 4
20
1
1
0
1
÷ 1
÷ 8
÷ 4
21
1
1
VDD/2
0
÷ 1
Off (high-z)
÷ 8
22
1
1
VDD/2
VDD/2
÷ 1
÷ 1
÷ 8
23
1
1
VDD/2
1
÷ 1
÷ 2
÷ 8
24
1
1
1
0
÷ 1
÷ 4
÷ 8
25
1
1
1
VDD/2
÷ 1
÷ 8
÷ 8
26
1
1
1
1
÷ 1
Off (high-z)
÷ 16
27
VDD/2
0
0
0
÷ 1
÷ 1
÷ 16
28
VDD/2
0
0
VDD/2
÷ 1
÷ 2
÷ 16
29
VDD/2
0
0
1
÷ 1
÷ 4
÷ 16
30
VDD/2
0
VDD/2
0
÷ 1
÷ 8
÷ 16
Rsv
VDD/2
1
VDD/2
1
Reserved
Reserved
Reserved
Rsv
VDD/2
1
1
0
N/A
Low
Low
(1)
The LVPECL outputs are open-emitter stages. Thus, if the unused LVPECL outputs Y0, Y1, or Y2 are left unconnected, then the current
consumption is minimized and noise impact to remaining outputs is neglectable. Also, each output can be individually disabled by
connecting the corresponding VDD input to GND.
Copyright © 2008, Texas Instruments Incorporated
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