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MPC5645S 데이터시트(PDF) 104 Page - Freescale Semiconductor, Inc |
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MPC5645S 데이터시트(HTML) 104 Page - Freescale Semiconductor, Inc |
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104 / 146 page ![]() Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8 104 Freescale Semiconductor 4.18.2 Nexus Debug Interface Figure 19. Nexus Output Timing Table 54. Nexus Debug Port Timing1 1 JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at VDD = 3.0 V to 3.6 V, TA = -40 to 105 °C, and CL = 50 pF (Cl=30 pF on MCKO), with SRC = 0b10 for MCKO and 0b11 for others. Num Symbol C Characteristic Min Max Unit SpecID 1tMCYC CC2 2 Parameter values guaranteed by design. D MCKO Cycle Time 15 — ns A2.1 2tMDC CC2 D MCKO Duty Cycle 40 60 % A2.2 3tMDOV CC2 D MCKO Low to MDO Data Valid3 3 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 0.1 0.2 tMCYC A2.3 4tMSEOV CC2 D MCKO Low to MSEO Data Valid3 0.1 0.2 tMCYC A2.4 5tEVTOV CC2 D MCKO Low to EVTO Data Valid3 0.1 0.2 tMCYC A2.5 6tEVTIPW CC2 D EVTI Pulse Width 4 — tTCYC A2.6 7tEVTOPW CC2 D EVTO Pulse Width 1 — tMCYC A2.7 8tTCYC CC2 D TCK Cycle Time4 4 The system clock frequency needs to be three times faster that the TCK frequency. NOTE Nexus Dual Data Rate is not supported. The timings are mentioned for dedicated pins on 416BGA. The max value for #2, 3 and 4 above, are 0.3 of tMCYC for shared nexus ports. 100 — ns A2.8 9tTDC CC2 D TCK Duty Cycle 40 60 % A2.9 10 tNTDIS, tNTMSS CC 2 D TDI, TMS Data Setup Time 25 — ns A2.10 11 tNTDIH, tNTMSH CC2 D TDI, TMS Data Hold Time 5 — ns A2.11 12 tJOV CC2 D TCK Low to TDO Data Valid 0 35 ns A2.12 1 2 4 5 MCKO MDO MSEO EVTO Output Data Valid 3 |
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