MPC5645S datasheet(112/146 Pages) FREESCALE

112 / 146 page

Qorivva MPC5645S Microcontroller Data Sheet, Rev. 8

112

Freescale Semiconductor

4.18.5

DRAM Interface

DDR Interface specification from ‘MCD - 32 Bit Automotive MCU - CMOS090LP2’ I/O Pad

Specification Revision 1.5 - May14th 2008.

This device supports SDR, DDR1, DDR2 half and full strengths, as well as LPDDR half and full speeds.

Table 58 shows the SRE settings for the different modes.

NOTE

The specs mentioned in the following table are preliminary.

Table 58. Pad mode configurations

ipp_sre[2:0]

Mode

000

1.8V LPDDR Half Speed

001

1.8V LPDDR Full Speed

010

1.8V DDR2 Half Strength

011

2.5V DDR1

100

Not supported

101

Not supported

110

1.8V DDR2 Full Strength

111

SDR

Table 59. LPDDR, DDR and DDR2 (DDR2-250) SDRAM timing specifications1 2

At recommended operating conditions with VDDE_DR of 5%

No.

Symbol

Parameter

Min

Max

Unit

CC Frequency of Operation (Clock Period)

N/A

125

MHz

1.1

tCK

CC Clock period

N/A

VIX-AC

CC MCK AC differential crosspoint voltage3

VDDE_DR

×0.5 –0.1

VDDE_DR

×0.5 +0.1

tCH

CC CK HIGH pulse width 3, 4

0.47

0.53

TCK

tCL

CC CK LOW pulse width 3, 4

0.47

0.53

tCK

tDQSS

CC Skew between MCK and DQS transitions4, 5

150

tOS(base)

CC Address and control output setup time relative to

MCK rising edge4, 5

(tCK/2) - 1000

N/A

tOH(base)

CC Address and control output hold time relative to

MCK rising edge4, 5

(tCK/2) +

1000

N/A

tDS1(base)

CC DQ and DM output setup time relative to DQS4, 5

(tCK/4) - 750

N/A

tDH1(base)

CC DQ and DM output hold time relative to DQS4, 5

(tCK/4) + 750

N/A

tDQSQ

CC DQS-DQ skew for DQS and associated DQ inputs4 -(tCK/4) - 600 (tCK/4) - 600

tDQSEN

CC DQS window start position related to CAS read

command3, 4, 5, 6, 7

TBD

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