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REF5050 데이터시트(PDF) 18 Page - Texas Instruments

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부품명 REF5050
상세설명  LOW DISTORTION DIGITAL-TO-ANALOG CONVERTER FOR SEISMIC
PDF  43 Pages
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DAC1282
SBAS490
– DECEMBER 2011
www.ti.com
Pulse Mode
In pulse mode, a fast responding, 5-bit pulse DAC is used to generate the output. The pulse DAC is designed to
approximate a linear-in-dB output function, allowing the generation of pulse test signals across all ranges. Two
registers are used to preset the DAC output. The SYNC pin is used to select one of the two registers. When
SYNC is low, the PULSA register value drives the DAC; when SYNC is high, the PULSB register value drives the
DAC. The pulse registers can be programmed to yield differential outputs from
–2.5 V to +2.5 V. Note that the
pulse levels scale with VREF and are independent of the analog gain settings. Table 6 lists the programmable
range of the pulse A and pulse B registers.
Table 6. Pulse Register Values
OUTPUT (V)(1)
PULSA[4:0], PULSB[4:0]
OUTPUT (V)(1)
PULSA[4:0], PULSB[4:0]
+2.50
01111
–0.020
11111
+1.88
01110
–0.029
11110
+1.25
01101
–0.039
11101
+0.938
01100
–0.058
11100
+0.625
01011
–0.078
11011
+0.469
01010
–0.117
11010
+0.312
01001
–0.156
11001
+0.234
01000
–0.234
11000
+0.156
00111
–0.312
10111
+0.117
00110
–0.469
10110
+0.078
00101
–0.625
10101
+0.058
00100
–0.938
10100
+0.039
00011
–1.25
10011
+0.029
00010
–1.88
10010
+0.020
00001
–2.50
10001
0
00000
(1)
VREF = 5 V. Ideal pulse mode differential output, values are rounded and exclude noise, offset, gain, and linearity errors.
Note that when pulse testing the ADC, the ADC digital filter time domain response has characteristic overshoot
and ringing. As a result of the ADC filter overshoot, input levels close to ADC full scale may cause clipping of the
ADC output code.
Digital Data Mode
In digital data mode, the DAC internal signal generator is bypassed and the DAC is driven instead by applying a
bitstream input. Arbitrary DAC output waveforms can be generated by application of custom digital data patterns.
The data format in this mode is ones-density modulated input at CLK/16 data rate (256 kHz). The input is applied
to the SW/TD input pin. The DAC1282 output in digital data mode is defined in Equation 3.
Digital Data Mode Differential Output = VOUTP
– VOUTN = VREF/2 × Gain × (TD – 50%)/25%
where:
VREF is 5-V nominal,
Gain is the analog gain (1/1 to 1/64),
TD is the bitstream ones-density from 25% to 75%.
(3)
18
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Copyright
© 2011, Texas Instruments Incorporated
Product Folder Link(s): DAC1282



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