t

SW/TD

t

TCSU

SW/TD

Sample

Next SW/TD

Sample

t

CTHD

t

SCSU

t

STDAT

t

TSOP

(Initial Output Update)

CLK

1

2

8

SW/TD

SYNC

Output

t

SYLW

(Output Reset)

9

12

24

400

(Output Settled)

t

SETL

DAC1282

www.ti.com

SBAS490

– DECEMBER 2011

SYNC

SYNC is a digital input used to synchronize the DAC1282 output.

In the digital data mode, the DAC input is a ones-density bitstream. In this mode, the SYNC pin synchronizes the

sampling of SW/TD digital data to the desired master clock cycle (CLK). When SYNC is low or high, the DAC

operates normally. When SYNC is taken from low to high, the DAC output is reset to zero and the sample instant

of SW/TD is reset to the eighth rising CLK edge that follows. The SW/TD is then regularly sampled on

subsequent 16 CLK intervals. After synchronization, the DAC output is not settled and achieves full settling 400

CLK periods later, as shown in Figure 39.

Figure 39. Digital Data Mode Synchronization

Table 10. Timing Characteristics for Figure 39(1)

SYMBOL

DESCRIPTION

MIN

TYP

UNIT

SYNC high to CLK high setup time

30

ns

SW/TD to CLK high setup time

30

ns

CLK high to SW/TD hold time

10

ns

SYNC low pulse width

2

CLK high after SYNC high to SW/TD sample time

8

SW/TD sample to output update

4

SW/TD period

16

SYNC high to fully-settled output

400

(1)

DVDD = 1.65 V to 3.6 V.

Copyright

© 2011, Texas Instruments Incorporated

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