DAC5687MPZPEP datasheet(12/75 Pages) TI1

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CLK2

* 0.5 ns

DAC5687-EP

SGLS333 – JUNE 2006

ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) (continued)

over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V,

IOVDD = 3.3 V, DVDD = 1.8 V, IOUT

FS = 19.2 mA (unless otherwise noted)

DIGITAL SPECIFICATIONS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CLOCK INPUT (CLK1/CLK1C, CLK2/CLK2C)

Duty cycle

50%

Differential voltage

0.5

TIMING PARALLEL DATA INPUT: CLK1 LATCHING MODES

(PLL Mode – See Figure 46, Dual Clock Mode FIFO Disabled – See Figure 48, Dual Clock Mode With FIFO Enabled – See

Figure 49)

Setup time, DATA valid to rising edge

ts(DATA)

0.5

of CLK1

Hold time, DATA valid after rising

th(DATA)

1.5

edge of CLK1

Maximum offset between CLK1 and

t_align

CLK2 rising edges – Dual Clock

Mode with FIFO disabled

Timing Parallel Data Input (External Clock Mode, Latch on PLLLock Rising Edge, CLK2 Clock Input, See Figure 44 )

Setup time, DATA valid to rising edge

ts(DATA)

72-

Ω load on PLLLOCK

0.5

of PLLLOCK

Hold time, DATA valid after rising

th(DATA)

72-

Ω load on PLLLOCK

1.5

edge of PLLLOCK

72-

Ω load on PLLLOCK. Note that

Delay from CLK2 rising edge to

tdelay(Plllock)

PLLLOCK delay increases with a lower

4.5

PLLLOCK rising edge

impedance load.

Timing Parallel Data Input (External Clock Mode, Latch on PLLLock Falling Edge, CLK2 Clock Input, See Figure 45)

Setup time, DATA valid to falling

ts(DATA)

High impedance load on PLLLOCK

0.5

edge of PLLLOCK

Hold time, DATA valid after falling

th(DATA)

High impedance load on PLLLOCK

1.5

edge of PLLLOCK

High impedance load on PLLLOCK. Note

Delay from CLK2 rising edge to

tdelay(Plllock)

that PLLLOCK delay increases with a

4.5

PLLLOCK rising edge

lower impedance load.

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