GRAYCHIP, INC.

- 19 -

JUNE 22, 1998

GC3021 MIXER AND CARRIER REMOVAL CHIP

DATA SHEET

This document contains information which may be changed at any time without notice

4.5

PLL CONTROL REGISTER

The phase lock loop (PLL) phase hold control and filter coefficients are stored in this register. The

suggested default is 028A (HEX) which sets A=10 and B=20 for acquisition, and 038e (HEX) which sets

A=14 and B=28 for tracking.

ADDRESS 5:

PLL_REG

BIT

TYPE

NAME

DESCRIPTION

0-4

R/W

A[0:4]

The 5 bit “A” coefficient. See Figure 7. The phase error

multiplied by 0 for A equal to 0.

5-9

R/W

B[0:4]

The 5 bit “B” coefficient. See Figure 7. The phase error

multiplied by 0 for B equal to 0.

10

R/W

EXT_ERROR

Use the EIN input as the error input to the PLL circuit.

EIN = 0 adds to the phase, EIN = 1 subtracts.

11-14

R/W

-

unused

15 (MSB)

R/W

PHASE_HOLD

The phase register tracks the value of the phase

increment when this bit is low and holds the last value

when this bit is high.

The A and B coefficients stored in this register are not used until the AB_SYNC is asserted as

described in Section 4.2.

4.6

FREQUENCY WORD REGISTERS

Registers 6 and 7 contain the 32 bit frequency tuning word. The frequency word is added into the

PLL output as shown in Figure 6. Bit 0 is the LSB, bit 31 is the MSB. The suggested default is zero.

ADDRESS 6:

FREQ_REG0

BIT

TYPE

NAME

DESCRIPTION

0-15

R/W

FREQ[0:15]

16 LSBs of the frequency word

ADDRESS 7:

FREQ_REG1

BIT

TYPE

NAME

DESCRIPTION

0-15

R/W

FREQ[15:31]

16 MSBs of the frequency word

The tuning frequency is specified using the formula:

where “Frequency” is the desired tuning frequency, and “clock rate” is the chip’s clock rate. The FREQ value

stored in these registers are transferred to the PLL circuit when the FREQ_SYNC is asserted as described

in Section 4.2.

FREQ

Frequency

Clock Rate

-----------------------------2

32

=