TFP410-EP

PanelBus

™ DIGITAL TRANSMITTER

SGLS344A − JULY 2006 − REVISED MAY 2011

13

POST OFFICE BOX 655303

DSEL=1

EDGE=0

DSEL=1

EDGE=1

DSEL=0

EDGE=0

DSEL=0

EDGE=1

Single-Ended

Clock Input

Mode

Differential

Clock Input

Mode (Low

Swing Only)

DE

D[11:0]

IDCK+

IDCK+

{(IDCK+) − (IDCK−)}

{(IDCK+) − (IDCK−)}

First Latch Edge

12-Bit, Dual-Edge Input Mode (BSEL = 0)

L = Low Half Pixel

H = High Half Pixel

Figure 6. Universal Graphics Controller Interface Options for 12-Bit Mode (Graphical Representation)

DSEL=0

EDGE=0

DSEL=0

EDGE=1

DSEL=1

EDGE=0

DSEL=1

EDGE=1

Single-Ended

Clock Input

Mode

Differential

Clock Input

Mode (Low

Swing Only)

DE

D[23:0]

IDCK+

IDCK+

{(IDCK+) − (IDCK−)}

{(IDCK+) − (IDCK−)}

First Latch Edge

24-Bit, Single-Edge Input Mode (BSEL = 1)

Figure 7. Universal Graphics Controller Interface Options for 24-Bit Mode (Graphical Representation)