TIBPLS506AC

13

× 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER

SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995

POST OFFICE BOX 655303

7

SR

SR

SR

SR

C Array

CLK

SR

SR

SR

tpd(3) CLK Internal to Output Response

tpd(2) CLK to Q Pin

tpd(1) I to Output Pin

tpd(b) or tpd(c)

CLK

Internal SRs

tmin(1) Min Clock Period

for This Path

tmin(2) Min Clock Period for This Path

tsu(b) or tmin(c)

tsu(1) I to Output S or R

Output SRs

CLK Internal

tsu(2) I to Internal S or R

tmin(3) Min Clock Period

for This Path

tsu(a) I to Internal S or R,

Data Through C Array

a

a, b

c

b, c

Dedicated Inputs

Dedicated Inputs

Output Pin

Feedback Lines

Figure 1. Timing Model