| 전자부품 데이터시트 검색엔진 |
|
TIBPLS506ACFN 데이터시트(PDF) 11 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TIBPLS506ACFN 데이터시트(HTML) 11 Page - Texas Instruments |
|
11 / 16 page ![]() TIBPLS506AC 13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 OR term loading As shown in Figure 3 and by the fmax calculations, fmax is affected by the number of terms connected to each OR array line. Theoretically, fmax is calculated as: fmax = 1 tsu ) tpd CLK to Q Since the setup time (input or feedback to S/R ↓) varies with the number of terms connected to each OR array line, (due to capacitance loading) fmaxwill also vary. Figure 3 illustrates the relationship between the number of terms connected per OR line and the setup time. Use Figure 3 to determine the worst-case setup time for a particular application. Identify the OR array line with the maximum number of terms connected. Count the number of terms and use the graph to determine the setup time. 15 14 12 11 10 19 13 020 40 60 17 16 18 Maximum Number of OR Terms Connected WORST-CASE SETUP TIME (input or feedback to SR ↓) vs ”OR” TERM LOAD 20 80 100 VCC = 4.75 V TA = 75°C Figure 3 |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |