SN8P1602AX datasheet(70/94 Pages) SONIX

70 / 94 page

SN8P1600

8-bit micro-controller

SONiX TECHNOLOGY CO., LTD

Page 70

Revision 1.94

MULTI-INTERRUPT OPERATION

In almost conditions, the software designer uses more than one interrupt requests. Processing multi-interrupt request

needs to set the priority of these interrupt requests. The IRQ flags of interrupts are controlled by the interrupt event. But

the IRQ flag “1” doesn’t mean the system to execute the interrupt vector. The IRQ flags can be set “1” by the events

without interrupt enable. Just only any the event occurs and the IRQ will be logic “1”. The IRQ and its trigger event

relationship is as the below table.

Interrupt Name

Trigger Event Description

P00IRQ

P0.0 trigger. OTP is falling edge.

TC0IRQ

TC0C overflow. (SN8P1602/1603)

TC1IRQ

TC1C overflow. (SN8P1604)

There are two works need to do for multi-interrupt conditions. One is to make a good priority for these interrupt

requests. Two is using IEN and IRQ flags to decide executing interrupt service routine or not. Users have to check

interrupt control bit and interrupt request flag in interrupt vector. There is a simple routine as following.

Example: How do users check the interrupt request in multi-interrupt situation?

ORG

; Interrupt vector

B0XCH

A, ACCBUF

; Store ACC value.

B0MOV

A, PFLAG

; Store PFLAG value

B0MOV

PFLAGBUF,A

INTP00CHK:

; Check INT0 interrupt request

B0BTS1

FP00IEN

; Check P00IEN

JMP

INTTC0CHK

; Jump check to next interrupt

B0BTS0

FP00IRQ

; Check P00IRQ

JMP

INTP00

; Jump to INT0 interrupt service routine

INTTC0CHK:

; Check TC0 interrupt request

B0BTS1

FTC0IEN

; Check TC0IEN

JMP

INT_EXIT

; Jump to exit of IRQ

B0BTS0

FTC0IRQ

; Check TC0IRQ

JMP

INTTC0

; Jump to TC0 interrupt service routine

INT_EXIT:

B0MOV

A, PFLAGBUF

; Restore PFLAG value

B0MOV

PFLAG,A

B0XCH

A, ACCBUF

; Restore ACC value.

RETI

; Exit interrupt vector

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