TMP100MDBVREP datasheet(2/22 Pages) TI1

2 / 22 page

TMP100−EP, TMP101−EP

DIGITAL TEMPERATURE SENSOR

WITH I2C INTERFACE

SGLS254A − JULY 2005 - REVISED APRIL 2010

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

functional block diagram

Diode

Temp.

Sensor

SDA

SCL

ADD0

V+

Temperature

GND

ADD1

ΔΣ

A/D

Converter

OSC

Config.

and Temp.

Serial

Interface

Control

Logic

TMP100

Diode

Temp.

Sensor

SDA

SCL

ADD0

V+

Temperature

GND

ALERT

ΔΣ

A/D

Converter

OSC

Config.

and Temp.

Serial

Interface

Control

Logic

TMP101

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage, V+

7.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range

−0.5 V to 7.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA

−55

°C to 125°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg

−65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction temperature, TJ

150

°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Thermal impedance,

θJA (See Note 1)

165

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature soldering

300

°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The thermal impedance,

θJA, for the DBV package is determined for JEDEC high−K PCB (JESD 51−7).

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