TMP100−EP, TMP101−EP

DIGITAL TEMPERATURE SENSOR

SGLS254A − JULY 2005 - REVISED APRIL 2010

13

POST OFFICE BOX 655303

APPLICATION INFORMATION

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device

that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA

line is stable low during the high period of the acknowledge clock pulse. Setup and hold times must be taken

into account. On a master receive, the termination of the data transfer can be signaled by the master generating

a not-acknowledge on the last byte that has been transmitted by the slave.

PARAMETER

FAST MODE

HIGH-SPEED MODE

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

SLCK operating frequency

0.4

3.4

MHz

Bus free time between STOP and START condition

600

160

ns

Hold time after repeated START condition. After this period, the

first clock is generated.

600

160

ns

Repeated START condition setup time

600

160

ns

STOP condition setup time

600

160

ns

Data hold time

0

0

ns

Data setup time

100

10

ns

SCLK clock low period

1300

160

ns

SCLK clock high period

600

60

ns

Clock/data fall time

300

160

ns

Clock/data rise time

300

160

ns

Table 13. Timing Diagram Definitions

P

S

S

P

SCL

SDA