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TNETA1575PGC 데이터시트(PDF) 30 Page - Texas Instruments |
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TNETA1575PGC 데이터시트(HTML) 30 Page - Texas Instruments |
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30 / 45 page ![]() TNETA1575 ATM SEGMENTATION AND REASSEMBLY DEVICE WITH PCI-HOST AND COPROCESSOR INTERFACES SDNS040C – MAY 1996 – REVISED JUNE 1998 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 operating characteristics (see Figure 12) control-memory interface – write operation NO. PARAMETER MIN MAX UNIT 1 td(CMAD) Delay time, from PCLK ↑ to CMAD15–CMAD0 valid 2 15 ns 2 td(CMDATA) Delay time, from PCLK ↑ to CMDATA31–CMDATA0 valid 5 15 ns 3 td(CMOE) Delay time, from PCLK ↑ to CMOE↑ 5 15 ns 4 td(CMWE)1 Delay time, from PCLK ↓ to CMWE↓ 5 15 ns 5 td(CMWE)2 Delay time, from PCLK ↓ to CMWE↑ 5 15 ns CMAD15- CMAD0 (output) CMOE (output) CMWE (output) CMDATA31- CMDATA0 (output) 3 2 Valid 4 5 1 PCLK (input) Valid Figure 12. Control-Memory Interface – Write Operation |
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