ThunderLAN

™ TNETE100

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

™

SPWS017B – APRIL 1995 – REVISED AUGUST 1996

24

POST OFFICE BOX 1443

MIN

TYP

MAX

UNIT

td(VDDH–FXTL1V)

Delay time from minimum VDD high level to first valid FXTL1V full swing period

(see Note 22)

100

ms

tw(H)

Pulse duration at FXTL1 high

13

ns

tw(L)

Pulse duration at FXTL1 low

13

ns

tt

Transition time of FXTL1

7

ns

tc

Cycle time, FXTL1

50

ns

Tolerance of FXTL1 input frequency

"0.01

%

† The FXTL signal may be implemented by either connecting a 20-MHz crystal across the FXTL1 and FXTL2 pins or by driving the FXTL1 from

a 20-MHz crystal oscillator module.

NOTE 22: This specification is provided as an aid to board design. This specification is not guaranteed during manufacturing testing.

FXTL1

VDD

td(VDDH–FXTL1V)

Minimum VDD High Level

tc

tw(H)

tw(L)

tt

tt

Figure 10. Crystal Oscillator Timing