TNETE211

ThunderLAN

™ TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR

100VG-AnyLAN

SPWS019 – MAY 1995

8

POST OFFICE BOX 655303

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels

are compatible with TTL devices.

Output transition times are specified as follows: For a high-to-low transition on either an input or output signal,

the level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low

is 0.8 V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level

at which the signal is said to be high is 2 V, as shown below.

The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically

1.5 ns.

0.8 V (low)

2 V (high)

test measurement

The test-load circuit shown in Figure 2 represents the programmable load of the tester pin electronics that are

used to verify timing parameters of TNETE211 output signals.

CL

IOH

VLOAD

IOL

Point

Test

Test

Under

Output

TTL

Where: IOL

= Refer to IOL in recommended operating conditions

IOH

= Refer to IOH in recommended operating conditions

VLOAD

= 1.5 V, typical dc-level verification or

0.7 V, typical timing verification

CL

= 18 pF, typical load-circuit capacitance

Figure 2. Test-Load Circuit