TNETE211

ThunderLAN

™ TO IEEE 802.12 PHYSICAL MEDIA DEPENDENT INTERFACE FOR

100VG-AnyLAN

SPWS019 – MAY 1995

9

POST OFFICE BOX 655303

POST OFFICE BOX 1443

PARAMETER

MIN

MAX

UNIT

tsu(MTx pins)

Setup time of inputs MTXD[0–3], MTXEN, MTXER (see Note 4)

10

ns

th(MTx pins)

Hold time of inputs MTXD[0–3], MTXEN, MTXER (see Note 4)

>0

ns

PARAMETER

MIN

MAX

UNIT

td(MRx pins)

MRCLK to output delay for MRXD[0–3], MRXDV, and MRXER (see Note 5)

0

15

ns

† Both MCRS and MCOL are driven asynchronously by the PMI.

NOTES:

4. MTXD[0–3] is driven by the reconciliation sublayer synchronous to the MTCLK. MTXEN is asserted and deasserted by the

reconciliation sublayer synchronous to the MTCLK rising edge. MTXER is driven synchronous to the rising edge of MTCLK.

5. MRXD[0–3] is driven by the PMI on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the edge

of MRCLK. MRXD[0–3] timing must be met during clock periods where MRXDV is asserted. MRXDV is asserted and deasserted

by the PMI on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the rising edge of MRCLK.

MRXER is driven by the PMI on the falling edge of MRCLK. It is sampled by the reconciliation sublayer synchronous to the rising

edge of MRCLK. MRXER timing must be met during clock periods when MRXDV is asserted.

td(MRx pins)

MRCLK

MRXD[0–3],

MRXDV,

MRXER

tsu(MTx pins)

th(MTx pins)

MTCLK

MTXD[0–3],

MTXEN,

MTXER

Figure 3. MII Transmit and Receive Timing