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CXD3017Q 데이터시트(PDF) 13 Page - Sony Corporation

부품명 CXD3017Q
상세설명  CD Digital Signal Processor with Built-in Digital Servo and DAC
PDF  117 Pages
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제조업체  SONY [Sony Corporation]
홈페이지  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXD3017Q 데이터시트(HTML) 13 Page - Sony Corporation

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CXD3017Q
§1. CPU Interface
§1-1. CPU Interface Timing
• CPU interface
This interface uses DATA, CLOK and XLAT to set the modes.
The interface timing chart is shown below.
• The internal registers are initialized by a reset when XRST = 0.
Note) Be sure to set SQCK to high when XLAT is low.
§1-2. CPU Interface Command Table
Total bit length for each register
Register
0 to 2
3
4 to 6
7
8
9
A
B
C
D
E
8 bits
8 to 24 bits
8 bits
20 bits
28 bits
24 bits
28 bits
16 bits
8 bits
16 bits
20 bits
Total bit length
750ns or more
D18
D19
D20
D21
D22
D23
750ns or more
Valid
CLOK
DATA
XLAT
Registers
D0
D1



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